This invention relates generally to semiconductor devices, and more specifically to a process for the formation of trench structures in a semiconductor integrated circuit.
The trend in semiconductor device fabrication towards increasing density of circuit components requires that ever smaller areas of the circuit be devoted to isolation of the circuit components and capacitive storage devices. The need to reduce the surface area used for circuit components such as isolation structures and large area capacitor devices has resulted in the development of structures vertically oriented with respect to the plane of the substrate surface. These vertical structures typically consist of some type of trench structure sunk into the semiconductor substrate, usually 3 to 5 microns deep, and are positioned intermediate to charge carrying components of adjacent transistors. The utilization of a trench structure enables the formation of a structure having a large volume while minimizing the amount of surface area consumed. The creation of a vertically oriented structure achieves the goal of minimal consumption of surface area, however, the vertical geometry does not by itself provide adequate electrical isolation from surrounding circuit components.
Metal-oxide-semiconductor (MOS), very large scale integration (VLSI) design requirements often require placement of a variety of circuit components in close proximity to each other. In certain cases these components must function independently of each other. Trench isolation structures, used to electrically isolate adjacent transistors, and large area trench capacitors used to store electrical charge must be fabricated in such a way as to minimize transistor performance degradation. The fabrication of a trench structure, in such a dynamic electrical environment, requires special techniques to minimize the formation of current leakage paths. Current leakage between source and drain regions of an adjacent transistor can occur in the area where the trench interfaces with the transistor gate. An additional problem is that of parasitic capacitor formation of the trench structure with highly doped source and drain regions of adjacent transistors.
In the case of an isolation trench, electrical isolation to at least the supply voltage, (commonly 5 volts), must be provided between integrated circuit components such as the source and the drain regions within a transistor, and between the source and drain regions of adjacent transistors. Typically an electrical isolation value of greater than twice the supply voltage is required to guarantee proper device performance. The main isolation related causes of transistor performance degradation are: subthreshold current leakage along the sidewall of the isolation trench near the transistor gate electrode; capacitive coupling between the source and drain regions and the isolation structure; and, the formation of a parasitic transistor after polycrystalline silicon (polysilicon) gate interconnects are formed which overlay the isolation structure. Each of these causes of transistor performance degradation must be addressed in order to fabricate a fully functional trench isolation structure.
FIG. 1 illustrates, in cross section, a trench structure according to the prior art showing the trench structure positioned in the substrate intermediate to two charge carrying elements. The elements shown in FIG. 1 comprise typical components of a portion of an integrated circuit structure. As noted above, an isolation trench is commonly used to provide electrical isolation between the source and drain regions of an MOS field effect transistor. A trench capacitor, for application in a DRAM cell, is often located in a similar substrate region. The trench is formed in an isolation region 11 of a semiconductor substrate 10. An insulation layer 14 overlies the surface of the substrate and a passivation layer 16 lines the walls of the trench. Using techniques well known in the art for a DRAM capacitor application, the trench is filled with a deposited conductive material 18, usually polysilicon, which is then etched back to form a continuous surface with insulation layer 14. In the case of an isolation structure, the trench can be filled with a dielectric material, such as silicon dioxide, as an alternative to a conductive material. During the etch back of excess fill material, as often occurs in this process, the etchant preferentially attacks material 18 along seam 20 yielding a surface similar to that shown in FIG. 1. The seam 20 and the depressed surface 22 are morphological characteristics resulting from the prior art processes used to deposit material 18 into trench 12 and etch back excess material. The presence of this depression can result in poor step coverage when a polysilicon gate interconnect overlying surface 22 is formed. The rough surface topography created by the surface depression can also result in an incomplete removal of the polysilicon during etching to form the gate interconnects. The unetched polysilicon remaining in the depression can provide an unwanted conductive channel between adjacent interconnects.
The semiconductor substrate 10 is subsequently processed to form source and drain regions 24 and 26 in substrate 10. The source and drain regions 24 and 26 consist of highly doped regions of substrate 10 which are usually created by ion implantation of an N or P type dopant atom such as phosphorus or boron. To adequately insulate transistor elements from each other, a means must be provided to further electrically isolate elements 24 and 26 from each other and from conductive material 18.
In the application of trench isolation structures to address electrical isolation requirements of adjacent transistors, and between source/drain regions of a single transistor, several problems must be solved. The most serious is sidewall channel current leakage long the gate of the transistor, i.e. into the plane of FIG. 1. A further problem is associated with the presence of a parasitic capacitor in which non-related source/drain regions 24 and 26 are capacitively coupled by extension of the depletion layers surrounding the source/drain regions in close proximity with trench 12. An additional problem occurs when a polysilicon gate interconnect is formed overlying surface 22. A parasitic transistor arises from the relative position of the source/drain region of adjacent transistors and the polysilicon interconnect over the trench isolation region 11. This problem is further compounded by forming the interconnect over an uneven surface caused by the fill and etch back technique previously described.
A number of methods have been used to address these problems. One technique is to first form an isolation region of thick silicon dioxide, normally to a thickness of about 800 nanometers, using a conventional localized oxidation of silicon (LOCOS) process. A mask having a trench pattern is then critically aligned to the previously formed isolation region in order to form a trench in a central portion of the isolation region. The formation of a trench in a region of thick silicon dioxide provides a passivation collar around the perimeter of the upper portion of the trench. A commonly encountered problem when using this method is that the trench is mis-aligned in the isolation region such that the edge of the trench lies in close proximity to a source/drain region. The mis-alignment then defeats the insulation benefits of the passivation collar.
The fabrication of a trench structure having adequate electrical isolation characteristics becomes increasingly important as available chip surface area, that can be devoted to isolation, diminishes. Previous fabrication methods have not totally addressed the problems associated with parasitic device action and topographical discontinuity. Accordingly, a need exists for a trench structure that is self aligned to the isolation region in a semiconductor substrate such that an isolation region of uniform dimension can be provided around the perimeter of the trench. A further need exists for a trench structure having a smooth surface topography that will allow a transistor interconnect to be evenly overlaid.